The present invention relates to a data writing technique employed for non-volatile memories, more particularly to a technique to be applied effectively to a method for reducing the variation of writing characteristics of MONOS (Metal Oxide Nitride Oxide Semiconductor) memory cells.
A flash memory that uses floating gate memory cells is widely known as a non-volatile memory in which data can be rewritten electrically. So far, there have been proposed various types of MONOS type memory cells to meet such requirements in the market as power saving and faster data writing.
For example, there is a MONOS memory cell in which a voltage (ex., about 0.77V) slightly higher than the threshold voltage of the word gate (control gate) is applied to the object word line so as to limit the data writing current to about 10 ìA (refer to the patent document 1). In other words, the data writing current is controlled by the voltage of the word gate. In that connection, the bit line voltage at data writing is fixed at about 0V.
There is also a floating gate type memory cell, which suppresses variation of writing characteristics (refer to the patent document 2).
In this case, a local bit line is connected to the two diffusion layers of the AG-AND (Assist Gate AND) type memory cell respectively and a switch is provided at the connection between the local bit line and a global bit line and between the local bit line and a common source line respectively.
At data writing, a voltage of about 4V is charged to the parasitic capacity of the memory gate side local bit line from the global bit line, and the global bit line is disconnected from the memory gate side local bit line by the switch.
After that, the assist gate side local bit line is connected to the common source line to transfer the charges stored in the memory gate side local bit line to the memory cell, thereby causing SSI (Source Side channel hot electron Injection) to occur so as to write data in the object one-bit memory cell.
Consequently, even when the threshold voltage of the assist gate MOS transistor is varied, the charges used to write data comes to be fixed. The variation of data writing characteristics is thus suppressed.
[Patent Document 1] Official Gazette of Japanese Unexamined Patent Publication No. 2001-148434
[Patent Document 2] Official Gazette of Japanese Unexamined Patent Publication No. 2002-197876